ARCH(3)                                                   ARCH(3)

          arch - architecture-specific information and control

          bind -a #P /dev

          This device presents textual information about PC hardware
          and allows user-level control of the I/O ports on x86-class

          Reads from cputype recover the processor type and clock rate
          in MHz.  Reads from archctl yield at least data of this

               cpu AMD64 2201 pge
               pge on
               coherence mfence
               cmpswap cmpswap486
               i8253set on
               cache default uc
               cache 0x0 1073741824 wb
               cache 0x3ff00000 1048576 uc

          Where `AMD64' is the processor type, `2201' is the processor
          speed in MHz, and `pge' is present only if the `page global
          extension' capability is present; the next line reflects its
          setting.  `coherence' is followed by one of `mb386',
          `mb586', `mfence' or `nop', showing the form of memory bar-
          rier used by the kernel.  `cmpswap' is followed by
          `cmpswap386' or `cmpswap486', reflecting the form of `com-
          pare and swap' used by the kernel.  `i8253set' is a flag,
          indicating the need to explicitly set the Intel 8253 or
          equivalent timer.  There may be lines starting with `cache'
          that reflect the state of memory caching via MTRRs (memory-
          type region registers).  The second word on the line is
          `default' or a C-style number which is the base physical
          address of the region; the third is a C-style length of the
          region; and the fourth is one of `uc' (for uncachable), `wb'
          (write-back), `wc' (write-combining), `wp' (write-

     ARCH(3)                                                   ARCH(3)

          protected), or `wt' (write-through).  A region may be a sub-
          set of another region, and the smaller region takes prece-
          dence.  This may be used to make I/O registers uncachable in
          the midst of a write-combining region mostly used for a
          video framebuffer, for example.  Control messages may be
          written to archctl and use the same syntax as the data read
          from archctl. Known commands include `cache', `coherence',
          `i8253set', and `pge'.

          Reads from ioalloc return I/O ranges used by each device,
          one line per range.  Each line contains three fields sepa-
          rated by white space: first address in hexadecimal, last
          address, name of device.

          Reads from irqalloc return the enabled interrupts, one line
          per interrupt.  Each line contains three fields separated by
          white space: the trap number, the IRQ it is assigned to, and
          the name of the device using it.

          Reads and writes to iob, iow, and iol cause 8-bit wide, 16-
          bit wide, and 32-bit wide requests to I/O ports.  The port
          accessed is determined by the byte offset of the file

          Reads and writes to msr go to the P4/P6/Core/Core2/AMD64

          Reads and writes to ec transfer bytes from and to the embed-
          ded controller.

          Reads from acpitbls return a concatenation of system ACPI
          tables. Each table is prefixed with a fixed size header that
          gives the name sigature and size of the table (see section
          5.2.6 System Description Table Header in the ACPI specifica-

          The following code reads from an x86 byte I/O port.

               inportb(unsigned port)
                   uchar data;

                   if(iobfd == -1)
                       iobfd = open("#P/iob", ORDWR);

                   seek(iobfd, port, 0);
                   if(read(iobfd, &data, sizeof(data)) != sizeof(data))
                       sysfatal("inportb(0x%4.4ux): %r", port);
                   return data;

     ARCH(3)                                                   ARCH(3)